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Chapter 2Background and Related Work
This chapter discusses background concepts and related work. As mentioned in Chapter 1, FPGA interconnect scaling is of concern. To provide more insight into this issue, trends in wire scaling and an overview of field-programmable gate array (FPGA) architectures are presented.Afterward, FPGA interconnect scalability is discussed, applying the presented wiring trends to FPGA architecture. To reduce the penalties of FPGA interconnect scaling, this thesis proposes the use of wire emulation as a means for cross-chip communication. This thesis uses the term “wire emulation” to describe techniques that realize the functionality of conventional wire interconnection resources. To this end, previous work in wire emulation technology, both in FPGAs and in ASICs, are lastly discussed.
Wire Scaling
Semiconductor manufacturing process advancements have allowed the manufacturing of deep sub-micron features on integrated circuits. With smaller feature sizes, IC designers can implement current designs in a smaller footprint and achieve gate delay reductions, allowing for the addition of new features while maintaining the original die size. As gate performance increases with scaling, only some wires will scale, causing a mismatch in scaling performance. The following discussion presents a basic overview of wire scaling issues.Local wires are those used to interconnect gates at the lowest logical primitive level. These wires are found on the first several metal layers of the die, and tend to be small in width and pitch (center to center distance between two wires). Since gates get smaller with scaling, the local wires between them get shorter, and therefore roughly scale with gates. On the other hand, global wires, those spanning across the length of the chip, will not scale with gates [3]; these wires tend to remain the same physical length while the density of logic that it spans increases. Therefore the delay of the global wire increases relative to gate delay under scaling. In addition, Rent’s Rule [4] shows that the number of connections outside of an area of logic is a function of logic density.Therefore, more global wires will be required to connect to other areas of the IC. Global wires are typically used for clock distribution and system level interconnects, and can be typically found at the higher metal layers of a die. In comparison to local wires, global wires must be implemented with larger pitch and wider metal. Larger wire pitch is important because it reduces the capacitive coupling and crosstalk between wires; the closer wires are together, the more susceptible they are to coupling and crosstalk noise. The crosstalk and noise scaling of long wires is discussed in [3]. Wider metal is important because cross-section size and length immediately affect wire resistance, and hence RC delay of a wire. Resistance (R) is inversely proportional to cross-section and grows quadratically with wire length [3], making unbuffered global wires undesirable. In addition, unbuffered global wires are predicted to double in delay relative to gate delay every technological progression [3]. Repeaters, typically implemented with inverters, can be used to segment a global wire into a set of smaller wires. The repeaters buffer the wire, resulting in linear delay growth in relation to wire length. The 2003 International Technology Roadmap of Semiconductors (ITRS) report offers a prediction of gate and wire performance scaling [5]. A graphic summary of their scaling prediction is shown in Figure 2.1. It is clearly shown that wires on metal layer 1 (local wires) will roughly follow the delay of gates while global wires will not, even with intermediate repeaters. Gate delay is expressed as fan out 4 or FO4, meaning the delay through a circuit consisting of an inverter driving four identical copies of itself. F04 is a useful metric because many CMOS logic circuits can be measured as having a delay multiple of FO4, which can hold true regardless of technology, temperature, and voltage.
Table of Contents
List of Figures
List of Tables
Introduction
1.1 Contribution
1.2 Thesis Organization
Background and Related Work
2.1 Wire Scaling
2.2 FPGA Architecture
2.2.1 Architectures
2.2.2 Interconnection and Logic Overhead
2.3 FPGA Scaling
2.4 Wire Emulation
2.4.1 FPGA Self-Reconfiguration
2.4.2 Network-on-Chip
FPGA Architecture Enhancement
3.1 Goals
3.2 Concept
3.3 Methodology
Wire Emulation Prototype
4.1 Overview
4.2 Concept
4.2.1 Configuration Memory
4.2.2 ICAP
4.3 System Design and Implementation
4.3.1 System FSM
4.3.2 Transports
4.3.3 ICAP Frame Reader
4.3.4 ICAP Frame Writer
4.3.5 ICAP Frame Copier
4.4 ICAP Multi-Frame Write
Results and Analysis
5.1 Prototype Wire Emulation System
5.1.1 Verification
5.1.2 Performance
5.1.3 Power
5.1.4 Multi-Frame Write Experiment
5.1.5 Improvements to Performance
5.2 Wire Emulation Architecture Analysis
5.2.1 Effects on FPGA Layout
5.2.2 Effects on FPGA Design Tools
Conclusions
6.1 Summary
6.2 Future Work
6.3 Conclusions
Bibliography
Vita
