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Electrical masking
Electrical masking occurs when a glitch fault is attenuated by subsequent logic gates due to the electrical properties and it may not have enough duration or amplitude to propagate to outputs, as seen in Fig. 3.1. The attenuation is caused by two reasons [62]:
• Gate delay induced by switching time of transistor causes the increase of rise and fall time of the glitch.
• Short duration of a pulse may lead to the decline of its amplitude, since the gate may begin to turning o↵ before the output reaches its full amplitude.
It is possible to model the electrical masking in di↵erent ways, according to the source. For instance, the transient glitch caused by radiation e↵ects is modeled as simple trapezoidal or triangle waveform in many works [63–65].
The electrical masking plays an important role for fault masking. Reported by Wang et al., even for a small circuit with a logic depth of 5 stages, 138% overestimation has been observed without considering the electrical masking [66]. However, with the continuous scaling down of CMOS, the reduction in node capacitance and supply voltage reduces the e↵ects of electrical masking.
Temporal masking
Temporal masking, also referred as latching-window masking, indicates the fact that an fault arrives at the output latch at the time of latching rather than the clock transition (where the input value of a latch is captured). A glitch will cause a soft error when it is captured. The capture can occur when the glitch presents through out the whole latching window or overlap the latching window [62]. As shown in Fig. 3.2, the first glitch is perfectly eliminated by temporal masking, whereas the second one overlaps the clock transition time and leads to a soft error.
In practice, temporal masking can be evaluated as the probability of a glitch being captured, that associates to summation of the glitch width according to primary inputs [63].
As the temporal masking strongly depends on the clock frequency, the increase in operational frequency makes temporal masking contribute less and less to masking e↵ects.
Logical masking
Unlike the previously mentioned maskings, logical masking will keep stable with the technology scaling down. Logical masking appears when a fault occurs on non-sensitized paths of a circuit. Figure. 3.3 presents a simple logical masking on C17 circuit [67]. A fault occurs on a gate connecting to the fanout, which is masked before reach to the primary output. The strong dependence on circuit topology makes logical masking very hard to estimate.
When the circuit contains lots of reconvergent fan-out, the estimation will become a NP problem [68].
For a long time, logic circuits were assumed to be more fault resistant compared with memory cells with these masking e↵ects, especially for the transient faults induced by radiation e↵ects. However, the vulnerability to faults of combinational circuit have become severe with the dimension scaling down (see Fig. 3.4). Moreover, due to the decline of two other masking e↵ects caused by technology innovation, logical masking has became the major masking e↵ect in logic circuits. Thus, this thesis devotes therefore to the evaluation of logic circuit reliability with respect to logical masking.
Table of contents :
Acknowledgements
Abstract
List of Tables
List of Figures
List of Acronyms
R´esum´e fran¸cais
1 Introduction
1.1 Motivation
1.2 Report organization
2 Basics on reliability
2.1 Reliability and faults
2.1.1 Metrics of reliability
2.1.2 Faults classification
2.2 Fault sources
2.2.1 Aging e↵ects: NBTI and HCI
2.2.2 Radiation related e↵ects
2.2.3 Thermal noise
2.3 Fault-tolerant techniques
2.4 Conclusions
3 Reliability evaluation methodologies
3.1 Fault masking
3.1.1 Electrical masking
3.1.2 Temporal masking
3.1.3 Logical masking
3.1.4 Logical masking assessment
3.2 Masking analysis methods
3.2.1 Modeling of transient fault
3.2.2 Single fault on iterative circuits
3.2.3 Multiple faults on CED circuits
3.3 Analysis of aging e↵ects
3.3.1 Aging-aware design flow
3.3.2 Case study: 65 nm adders
3.4 Conclusions
4 E↵ective design for reliability
4.1 E↵ective fault-tolerant design
4.1.1 Introduction
4.1.2 Case study: S-Box in AES
4.2 Hybrid fault-tolerant S-Boxes
4.2.1 Introduction
4.2.2 Hybrid architecture for S-Boxes
4.2.3 Cost evaluation
4.2.4 Reliability assessment
4.3 Conclusion
5 Conclusions and prospectives
5.1 Conclusions
5.2 Prospectives
A Binary adders
A.1 One-bit adder
A.2 Ripple carry adder
A.3 Carry-select adder
A.4 Carry look-ahead adder
A.5 Carry-skip adder
A.6 Parallel prefix adder
B Finite field arithmetic operator
B.1 Finite field
B.2 Addition on GF(2m)
B.3 Multiplication on GF(2m)
Bibliography
