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Electrical issues in low-dimensional structures
Low-dimensional structures have some interesting electrical phenomena such as an electron tunneling and a quantization of electronic states. The electron tunneling is a quantum mechanical phenomenon where a particle (e.g. an electron) can tunnel through a potential barrier at the quantum scale. It is used for the tunneling diode applications. On the other hand, the electron and its energy state are limited and quantized by the dimensionality. Electronic behaviors in a solid are determined by the density of state at the Fermi energy. The energy dispersion in a bulk and low-dimensional structures are illustrated in Figure 1.6 [27]. Many electrical and physical properties in low-dimensional structures are expected to have better performances for nano electronics. To achieve low-dimensional structures by top-down or bottom-up approaches, there are some practical issues which should be considered.
For low-dimensional structure devices with conventional CMOS technology, an important issue is short-channel effects. The short-channel effects induced a leakage current in the off-state thereby increase the power consumption for the idle state. To reduce the short-channel effects and obtain the better gate control, nanowire channels with a gate-all-around structure are seen as an ideal transistor channel [28]. According to the device scaling, the channel is approaching 1-D structures which have large surface/volume ratio. The large surface/volume ratio is advantageous for sensor applications but it can also affects the electronic transport due to surface effects. The surface roughness control is one of the difficulties for nanostructures with top-down process and it can be a source of trapping center of charge carriers or mobility degradation by scatterings. The electrical noise, especially 1/f noise, is another issue for device scaling. As decreasing the device size, the 1/f noise is expected to increase because the relative noise spectral density is inversely proportional to the effective size of devices [29], [30]. The 1/f noise in the drain current or gate voltage of a MOSFET has been an important role for analog circuits and RF applications which are related to the signal to noise ratio (SNR) and the phase noise of oscillators, respectively [31]. Many studies for nanotubes and nanowires have been reported to exhibit significant current fluctuations in the low-frequency regime [32-39].
On the other hand, a Schottky barrier between the metal and semiconductor is a notable issue when we make a device with bottom-up growth nanowires. In general, metal electrodes are commonly used in a nanowire device unlike conventional MOSFETs having source/drain contacts with degenerated doped silicon. It is due to the difference of preferred fabrication process with nanowires [40]. For this reason, the existence of Schottky barrier in nanowire devices is inevitable. These contacts can be improved after thermal annealing process but it still limits the device performance and disturbs the intrinsic properties of the nanostructures.
Linear extrapolation method
The most classical method is a linear extrapolation method, which is an old style but well-known, using a linear fit at the maximum transconductance, gm, max from ID-VGS characteristics at the linear region. At strong inversion, the drain current can be expressed as I D = W µ eff C (V −V )V DS − 1 V 2 (2.5).
where W is the channel width, L the channel length, and μeff the effective mobility. If VDS is small enough, Equation 2.5 can be simplified to Figure 2.2 Illustration of the linear extrapolation method for a commercial n-channel MOS transistor (HCF4007UB, a dual complementary pair plus inverter comprised of three n-channel and three p-channel enhancement type MOS transistors) at VDS = 0.1 V. I = W µ C (V − V )V (2.6).
At a constant of VDS, based on Equation 2.6, the current expects to appear a linear curve for ID-VGS characteristic but the actual curve is not linear because the effective mobility will be degraded at higher gate voltage. Therefore, a point to fit Equation 2.6 is the point where the transconductance gm (=dID/dVGS) reaches its maximum value. The threshold voltage can be found at the point of zero current in the linear fit drawn with the ID-VGS curves focusing on the gate voltage at the gm, max as illustrated in Figure 2.2. However, the linear extrapolation method is sensitive to the series resistance and mobility degradation.
Conductivity (or drift) carrier mobility
The conductivity mobility (μdrift) is derived from the simple relation between mobility and electrical conductivity σ that is the proportional to the product of the mobility and carrier concentration in semiconductor materials. The conductivity is given by σ = q(nµdrift ,e + pµdrift,h ) (2.15).
where n is the electron density, μdrift,e the electron mobility, p the hole density, and μdrift,h the hole mobility. The conductivity mobility is simple and easy to find but the majority carrier density is needed to obtain the accurate conductivity mobility. It is useful to characterize for the intrinsic property of materials.
Hall carrier mobility
The Hall measurement is a well-common method based on Hall Effect to obtain the mobility, carrier type, and carrier concentration in material. The Hall Effect is a phenomenon to produce a potential difference (Hall voltage, VH) perpendicular to the magnetic field and current when the magnetic field applied to the electrical conductor perpendicular to the current flow direction. As shown in Figure 2.6, it shows a schematic illustration of Hall Effect in a p-type conductor and the force causing Hall voltage is given by the vector expression F = q(E + ν × B) (2.16).
MOSFET carrier mobility
In general, the conductivity and Hall mobilities are for bulk. In the case of MOSFETs, the surface is relatively important and the mobility is easily affected by various scatterings such as ionized impurity scattering, phonon scattering, and so on. Considering these scatterings, the total mobility is limited by the lowest mobility according to Mathiessen’s rule. Therefore the method to extract the mobility only for MOSFET structures has been used. Effective mobility and Field-effect mobility are well-known terminology widely used for various material devices as well as silicon MOSFETs. Let consider an n-channel MOSFET of gate length L and width W. The drain current is simplified for the basic MOSFET operation as I = g ⋅V = W µ Q V (2.18).
where gd is the drain conductance, μeff the effective mobility and Qi the inversion channel charge density (C/cm2). To extract the exact value of effective mobility, the inversion charge density Qi is important and it can be determined in two different ways. One is a simple approximation with Qi = COX (VGS − VTH ) (2.19).
and the other is a direct measurement of Qi from the capacitance measurement (refer Chapter 2.6). The direct measurement of charge carriers is better than the approximation to extract the value of effective mobility. However, it is not convenient in many ways such as a necessity of additional C-V measurement and several capacitance effects (e.g. an overlap capacitance) depending on the device structure. For this reason, the approximation method is well used for the comparison for the number of devices and the capacitance measurement is recommended to obtain the more precise value of mobility.
For the effective mobility, the drain voltage is typically recommended about 50~100 mV as small as possible considering the uniformity of inversion charge carriers from source to drain. The definition of effective mobility is given by WQi µeff = gd L (2.20)
Table of contents :
Chapter 1 Introduction to low-dimensional structures
1.1 Scaling overview
1.2 1-D and 2-D structures
1.3 Top-down vs. Bottom-up approaches
1.4 Electrical issues in low-dimensional structures
1.5 Outline of the thesis
Chapter 2 Electrical properties for FET structures
2.1 Introduction
2.2 Threshold voltage
2.2.1 Linear extrapolation method
2.2.2 Second derivative method
2.2.3 Y-function method
2.3 Carrier Mobility
2.3.1 Conductivity (or drift) carrier mobility
2.3.2 Hall carrier mobility
2.3.3 MOSFET carrier mobility
2.4 Series and contact resistances
2.5 Subthreshold swing
2.6 Capacitance
2.7 Summary
Chapter 3 Low-frequency noise characterization
3.1 Background: Definition and concepts
3.2 Fundamental noise sources
3.2.1 Thermal noise
3.2.2 Shot noise
3.2.3 Generation-Recombination (g-r) noise
3.2.4 Random-Telegraph-Signal noise
3.2.5 1/f noise
3.3 1/f noise models for FET structures
3.3.1 Hooge mobility fluctuation model
3.3.2 Carrier number fluctuation model
3.3.3 Carrier number fluctuation with correlated mobility fluctuation model
3.4 Noise measurement system configuration
3.5 Summary
Chapter 4 Multi-Gate MOSFET
4.1 Background: From planar to 3-D structure
4.2 FinFETs
4.2.1 Device structure
4.2.2 Electrical characterization at the fin width variation
4.2.3 Electrical characterization of the length dependence
4.2.4 Device simulation for the fin width dependence
4.3 Junctionless FETs
4.3.1 Device structure
4.3.2 DC characteristics
4.3.3 LF noise characteristics
4.4 Summary: Surface vs. Bulk conduction
Chapter 5 Nanowire and Nanotube
5.1 Background: Toward 1-D structures
5.2 3-D stacked Si and SiGe nanowires
5.2.1 Mobility enhancement – strain effect
5.2.2 Device structure
5.2.3 C-strained and un-strained SiGe nanowire p-type FETs
5.2.4 Noise comparison between Si and SiGe nanowire n-type FETs
5.3 Nanotubes and nanowires based on Bottom-up approach
5.3.1 Metal-semiconductor junctions in multi-walled carbon nanotubes
5.3.2 Quality index for metal contacts – GaN nanowire
5.4 Summary: Impact of channel strain and metal contact
Chapter 6 Graphene
6.1 Physical Backgrounds
6.1.1 Electronic structure and carrier transport
6.1.2 Research trends of graphene
6.2 Device structure of graphene field effect transistors
6.3 Electrical properties and low-frequency noise in G-FETs
6.3.1 Typical I-V characteristics & Length dependence
6.3.2 Mobility scatterings on the SiO2 substrate
6.3.3 LF noise characteristics
6.4 Summary
Chapter 7 Conclusions & Perspectives
References
