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CMOS scaling down and Short channel effects
In order to achieve various benefits and proper function of electric circuits from scal-ing the devices, the other structure parameters should be correctly scaled together with channel length reduction. These are summarized in Table 1.1 [8]. For an instance, if the channel length is reduced by a factor of k, other geometrical parameters such as thickness of gate−oxide, width and source/drain junction depth should be scaled with 1/k.
Following these initial rules, doping concentration should increase with k due to the reduction of depletion width. In addition, the power supply voltages should be decreased with k for sustaining internal electric field to the next generation of CMOS technology, appropriately. Unfortunately, in the case of practical technology, these scaling rules could not be followed due to a combination of physical and system−related limitations. It is obvious when we consider the power supply voltages in the industry. For the 250nm, 180nm and 130nm transistors they were 2.5V, 1.8V and 1.3V in the industry, respectively. This trend was good in term of the scaling rules. However, for the 90nm and 45nm transistors, the industry used 1.2V and 0.9V instead of 0.9V and 0.45V. But at the same time, a diversity of problems arose, such as hot carrier effects, drain induced barrier lowering (DIBL), short channel effects and velocity saturation, which re-sults in deviation of electric devices from their ideal operation [8,10,11].
Advanced CMOS technology
In order to suppress the short channel effects and hot carrier effects, and keep the de-vices scale down, the device channel engineering was introduced such as lightly doped drain (LDD), pocket or halo implant. Furthermore, many kinds of technologies have been introduced like multiple gate device, high−k and metal gate, SOI device, strain engineering and alternative channel engineering. Fig. 1.3 is the overview of advanced CMOS technology [10,12].
High−k and Metal gate (HKMG)
As aforementioned, the physical thickness of gate oxide (tox) has been initially de-creased for proper scaling down. However, while silicon dioxide was used as gate oxide, tox reached a limit, around 1.1nm in 2006. Indeed, gate current became unacceptably high as expo-nentially increases with tox reduction. It was a serious problem in terms of device life, standby power consumption and reliability. Thus, the researchers sought other materials with a higher dielectric constant, high−k materials, for increasing tox and replacing SiO2. The equivalent ox-ide thickness can be derived as
As listed in Table 1.2 [13], various high−k materials have been studied for the future technology. Moreover, as compared to SiO2 and HfO2, there are intermediate solutions for compromising between defect density and high−k, such as oxynitrides (SiON) and hafniumsilicates (HfSiON).
The metal gate was introduced for blocking of added capacitance from poly−Si since it can act as the additional capacitor which is connected with gate oxide in series. Furthermore, the use of metal gate can suppress dopant penetration through the gate oxide and Fermi level pinning [10]. For controlling threshold voltages, the metal gate electrode should be properly chosen in terms of work function. For the first time, these high−k and metal gate (HKMG) stack were introduced in 45nm−node. In short, Fig.1.4 summarizes why the HKMG technology was needed, and obstacles and solutions of adapting the HKMG to 45nm−node [14].
Strain engineering
The strain engineering in CMOS technology has been introduced to enhance mobility. The mismatch of lattice constants in heterostructures creates local deformations (i.e. compres-sive or tensile strain) [8]. The strain engineering has been a striking method for enhancing the carrier mobility of the CMOS technology at 90nm−node in 2003 and beyond. One general method is to get a tensile strain in Si channel on the relaxed SiGe virtual substrate since SiGe has larger lattice constant than that of Si. As shown in Fig. 1.5, the tensile strain induces varia-tions of the energy band spectrum, which results in reduction of effective electron mass and suppression of inter−band scattering since the curvature of energy band spectrum in k space presents effective mass and there are splits of energy bands. Thus, the tensile strained Si chan-nel can have higher electron mobility than unstrained ones. In the SiGe channel in pMOSFET, the compressive strain has a positive effect on hole mobility [15]. It is worth noting that the strain engineering is the trade−off between mobility enhancement and dislocation formation. In other words, there is a certain limitation in terms of lattice mismatch.
Multiple−gate and tridimensional gate devices
A variety of new gate structures have been introduced with the aim of better control-ling the potential in the channel. They have been proposed in order to eliminate the short chan-nel effects and punch through from source to drain in MOSFETs. Some of these architectures are using independent gates (e. g. double−gate structures). Others are using 3D gates with the aim of wrapping the channel as much as allowed by the fabrication technology such as FinFETs, gate−all−around FETs and Omega gate FETs. They are sometimes named under the general term of “multiple−gate” structures in order to bring attention on the fact that the channel is no longer a simple planar channel but can be viewed as the addition of several channels in parallel, some with different crystal orientations and different dielectric thicknesses for gate control. Re-cently, these device architectures have also been studied with SOI and Silicon substrates as shown in Fig. 1.6 [17].
The multiple gate transistors can bring high on−current, reduction of DIBL and supe-rior properties of on−off operations since the increase of gate number can improve electrostatic control of devices. Quantitatively, it was reported that the planar FD−SOI devices require 1/3 of gate length as a channel thickness (L/3 > tsi) to control short channel effects while the double gate FinFETs need 2L/3 > tsi [10,16]. In the CMOS industry, the FinFET architecture was intro-duced at 22nm−node in 2011 by Intel. Intel expected an outstanding combination of perfor-mance and energy efficiency by 3D tri−gate transistors. In addition, these ultra−low power tran-sistors could be widely used in portable electric devices like cell phones and tablets. There are some challenges in the viewpoint of economic and technological aspects like high process complexity and low yield as compared with FD−SOI and bulk CMOS technologies even though FinFETs have tremendous advantages such as enhancement of performance and varia-bility due to reduction of channel doping concentration and vertical field [17,18].
Table of contents :
Chapter 1
Context of the work
1.1 The context of CMOS technology
1.1.1 CMOS scaling down and Short channel effects
1.2 Advanced CMOS technology
1.3 Devices under study
1.4. Dissertation scope and outline
Chapter 2
Theoretical and experimental backgrounds
2.1 Parameter extraction methods for MOSFETs
2.1.1 Mobility
2.1.2 Series Resistance from the Y−function method
2.1.3 Threshold voltage (VT)
2.1.4 Subthreshold swing (SS)
2.2 Magnetoresistance
2.2.1 Principle of magnetoresistance mobility extraction
β.β.β Comparison between eff, H and MR
2.3 Low frequency noise
2.3.1 Fundamental noise sources
Chapter 3
Full split C−V method for parameter extractions
3.1 Introduction
3.2 Experiment details
3.3 Results and Discussions
3.3.1 Refinement of gate−to−channel capacitance analysis
3.3.2 Gate−to−bulk capacitance exploitation in UTBB FDSOI
3.4 Conclusions
Chapter 4
In depth characterization of carrier transport in 14nm FD−SOI CMOS transistors
4.1 Introduction
4.2 Experiment details
4.3 Results and Discussions
4.3.1 General transport characteristics of NMOS devices and methodologies
4.3.2 Transport properties of PMOS devices
4.4 Conclusions
Chapter 5
Low temperature characterization of mobility in 14nm FD−SOI CMOS devices under interface coupling conditions
5.1 Introduction
5.2 Experiment details
5.3 Results and Discussions
5.3.1 Long channel
5.3.2 Gate−length variations
5.3.2 Short channel in interface coupling conditions
5.4 Conclusions
Chapter 6
Magnetoresistance mobility characterization in advanced FD−SOI transistors
6.1 Characterization of magnetoresistance in linear regime of FD−SOI nMOS devices
6.1.1 Introduction
6.1.2 Experiment details
6.1.3 Results and discussions
6.1.3.1 μMR extraction in long channel at 300K
6.1.3.2 Influence of temperature and gate length variations
6.1.3.3 Additional mobility induced by high−k layer
6.1.3.4 Mobility degradation factor
6.1.4 Conclusions
6.2 Experimental and theoretical investigation of magnetoresistance from linear to saturation regime in 14−nm FD−SOI MOS devices
6.2.1 Introduction
6.2.2 Experiment details
6.2.3 Physical compact model of high field transport with magnetoresistance effect
6.2.4 Results and discussions
6.2.4.1 μMR extraction procedure
6.2.4.2 Modeling of I−V and MR in all operation regimes
6.2.4.3 Carrier velocity extraction
6.2.4.4 Comparative analysis of carrier velocity
6.2.5 Conclusions
Chapter 7
Low−frequency noise characterization of 14nm−node FD−SOI CMOS transistors
7.1 Introduction
7.2 Experiment details
7.3 Results and Discussions
7.3.1 Noise characterization in the linear regime
7.3.2 Noise characterization from the linear to saturation regime
7.4 Conclusions
Chapter 8
Conclusions
