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Gate stack technology for 14/28 nm FDSOI MOSFET devices
This chapter introduces the gate stack technology for a MOSFET device of the 14 and 28 nm FDSOI technology. Section 1.1 describes the working operation of a MOSFET device and its various performance parameters and how they can be tuned by the various charges, interface states and dipoles present in the gate stack. Section 1.2 describes the need for different layers consisting the HKMG stack and their processes, i.e. the interlayer, high-k and the metal gate. Special attention has been paid to the deposition of TiN, La and Al by the RF-PVD method, and their various process parameters have been discussed. Then, the introduction of La and Al for VT engineering into the HKMG stack has been discussed.
Section 1.3 describes the process flow used to manufacture the MOS devices used in this work, and its simplification for capacitance devices. Section 1.4 presents the various contributions to VT variability and special attention has been paid to the contribution of the metal gate microstructure to VT variability. In section 1.5, a brief introduction of the NBTI, PBTI and TDDB reliability has been given. This describes the state of the art and the various mechanisms and models that exists presently.
MOSFET device
MOSFET operation
Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is based on the principle of the field effect [1], which is the modulation of charge density in a material by an electric field applied perpendicularly to its expected flow. In a MOSFET the charge is controlled at the semiconductor surface, called the channel. A MOSFET is a four-terminal device consisting of: source, drain, gate and substrate as shown in Figure 1.1. Modulation of charge carriers in the semiconductor channel is governed by the polarization of gate (VG) and substrate (VB) through an insulating layer (the dielectric layer) by capacitive coupling. After their generation, carrier’s transportation in the channel is controlled by potential difference (VD) between the two charge reservoirs (source and drain) establishing a drain current ID. The transistor thus behaves like a switch. It is in an ‘OFF’ state (VG = 0 V) for which the current between source and drain is very low and in an ‘ON’ state for which VG is equal to VD, allowing the passage of current ION. The threshold voltage (VT) is the minimum gate-to-substrate voltage difference that is needed to create a conductive channel between the source and drain terminals.
The MOS capacitor is the simplest MOS structure and is composed of a p-type (for NMOS) or n-type (for PMOS) doped silicon substrate, a gate oxide and a metal layer. When the different layers constituting the MOS structure are brought into contact, an alignment of Fermi levels of metal (EFM) and semiconductor (EFSi) appears. As a result, a unique thermodynamic system is formed which is characterized by a single Fermi level (Figure 1.2). Then, an electrostatic potential, called contact potential (VC), is generated following the alignment of the Fermi levels. It is expressed by:
VC = M − Si 1.1 where q M corresponds to the difference between the metal Fermi level and its vacuum level, q Si corresponds to the difference between the semiconductor Fermi level and its vacuum. q F is the difference between the intrinsic Fermi level of silicon and the resulting Fermi level. In addition, a bending of energy bands is directly driven by the contact potential in the semiconductor (VSi) and in the oxide (VOX) and at VG = 0 V their relationship is given by:
VC = M − Si = – (VOX + VSi) 1.2
When a gate bias VG is applied, then equation 1.2 becomes:
VG = M − Si + VOX + VSi 1.3
Assuming that the oxide is perfect (absence of charges), the oxide potential drop Vox will be linear. So, we can express it using Gauss theorem from the charge QSi created in the semiconductor: VOX /TOX = -QSi/εox 1.4
where QSi is the charge in the semiconductor and TOx is the oxide thickness. The relationship between QSi and VSi can be described by the Poisson equation for electrostatics, according to classical electrodynamics [1]. However, for ultra-thin oxide thicknesses and low field strengths, such interactions are better described by quantum Poisson-Schrodinger simulations described in chapter 2.
The charges induced in the semiconductor may be of three types: majority carriers, minority carriers and depletion charge. These charges can be controlled by the voltage applied to the gate VG, specifically by VSi. For a p-type semiconductor substrate and with a NMOS transistor, the following regimes occurs depending on the applied VG:
• VSi < 0: Accumulation regime. Majority carriers are attracted to the surface of the semiconductor and their density becomes larger than that in the substrate volume. The transistor is in the “OFF” state (Figure 1.3a).
• VSi = 0: Flat band condition. The flat band voltage (VFB) is the bias condition of the gate VG at which there is no charge in the substrate. At this condition the applied potential VG equals the contact potential VC. There is no bend bending at the Si interface, i.e VSi = 0, and the concentrations of minority and majority carriers are constant throughout the substrate (Figure 1.3b).
• 0 < VSi < F : Depletion regime. Majority carriers are reduced at the interface and minority carriers starts to increase at the semiconductor interface. An area depleted of carriers is created near the surface (Figure 1.2)
• F < VSi < 2 F : Weak inversion or subthreshold regime. Minority carrier density starts to increase and equals the majority carriers at the surface, but still remains low compared to that of the majority carriers in the substrate volume. Transistor is in the « OFF » state or weak inversion under threshold voltage (Figure 1.4a).
• 2 F < VSi : Strong inversion regime. The transistor is in the « ON » state. Minority carrier density becomes greater than the majority carrier concentration in the substrate volume. In this case, a minority carrier channel is formed between the source and the drain on the surface of the semiconductor and is called the inversion channel (Figure 1.4b).
The threshold voltage VT of a MOS can be defined as the gate voltage VG such that the condition VSi = 2 F is satisfied. Thus we obtain as follows: VT = M − Si + 2 F – √ (4εSiqNSiΦF)/COX 1.5 where, εSi is the semiconductor permittivity, NSi is the substrate doping concentration (cm-3) and COX is the capacitance per unit area. In fact, if there is one unique VFB condition corresponding to semiconductor flatband at the interface, VT characterizing the onset of the transistor may find several definitions: such as specific surface potential VSi, certain channel current density at a certain drain voltage VD, maximum of transconductance, extrapolation to ID = 0 etc.
The heavily doped (n+ for NFETs and p+ for PFETs) source/drain regions, are used to make an ohmic contact with the conductive channel for |VG| >|VT|, so that a voltage difference between the source and the drain (VDS) will result in a current flow (IDS) of minority carriers (electrons for NFETs and holes for PFETs) from the positive voltage at the drain terminal to the negative voltage at the source (the polarity and current flow is the contrary for a PMOS). This current flow of minority carriers is also known as drive current and is one of the main MOSFET device performance parameters. In the « OFF » state, the drive current is very small (ideally zero) and in the « ON » state, it is a function of both VG and VD.
Metal-Oxide-Semiconductor gate stack properties
Gate dielectric capacitance and equivalent oxide thickness
Capacitance is the ability of a body to store an electrical charge on two electric conductors separated by a dielectric layer. When a potential difference V is applied to the conductors, an electric field develops across the dielectric, causing positive charge (+Q) on one plate and negative charge (-Q) on the other plate. The capacitance C is defined as C = Q/V. In a Metal-Oxide-Semiconductor capacitor, one of the plates is the metal gate and the other is the silicon substrate. The dielectric consists of the gate oxide with a relative permittivity εox (commonly known as the dielectric constant) and thickness TOX. Consequently, the gate dielectric capacitance per unit area (COX) can be expressed as follow: COX=ε0εox/TOX 1.6 where ε0 = 8.854.10-12 F/m is the vacuum permittivity.
SiO2 was the industry standard oxide material for MOS capacitance measurements. In order to compare different dielectric materials, and with respect to SiO2, the notion of EOT (Equivalent Oxide Thickness) has been introduced. EOT is the equivalent thickness of SiO2 oxide giving the same capacitance for any dielectric (usually a high-k dielectric) of physical thickness TOX and dielectric constant εox. The EOT is given by: EOT=TOX εsio2/εox 1.7
The capacitance is thus given by: Cox = ε0εsio2/EOT 1.8
The physical measurement of the nanoscale oxide thicknesses is difficult because it evolves during the manufacturing process and physical measurements reach their limit when thickness become close to the nanometer. The extraction of EOT constitutes a more accurate and relevant measurement to exploit the VFB variations with that of the oxide thickness. We will therefore express various equations in terms of EOT rather than the physical semiconductor oxide thickness.
Flat band voltage VFB
The flat band voltage (VFB) is the bias condition of the gate VG at which there is no charge in the substrate, leading to flat energy bands at the interface (VSi =0, QSi =0) (Figure 1.3 b). Thus the voltage associated with the applied potential is called the flat band voltage and is expressed as follows: VFB = M − Si + VOX 1.9
The term VOX, at flatband, is 0 for an ideal device (when no oxide charges or interfacial drops are present and Eq. 1.4 applies). For non-ideal cases, VOX is not equal to 0 and so VFB is influenced by oxide charges density and interfacial voltage drops such as dipoles. So for real devices it becomes a process dependent parameter, especially in bilayer high-k/SiO2 oxide structures that are currently being used in advanced MOSFETs.
There are generally 4 types of charges possible in a MOSFET device that can affect the VFB (Figure 1.5):
• The interface fixed charges Qfi, that can be located near the Si/SiO2 interface, high-k/SiO2 interface, metal/high-k layer [2]. Fixed oxide charges do not move or exchange charge with the underlying silicon and also do not change with the applied voltage.
• Bulk oxide charges Qbulk are the charges in the volume of the oxides and consists of the oxide trapped charges (Qot) and the bulk fixed charges (Qfb). Like interface fixed charges, these do not move or exchange charge with the underlying silicon [3].
• The interface trapped charges (Qit) are positive or negative charges located at the Si/SiOx interface. They are due to structural defects, oxidation-induced defects or dangling bonds at this interface. Unlike fixed charges or trapped charges, interface trapped charges are in electrical communication with the underlying channel and can thus be charged or discharged, depending on the Si surface potential VSi [3].
• Mobile ionic charges (Qm) are primarily due to positive alkali ions in the oxide such as Na+, K+ and Li+ [4], incorporated during device processing steps.
The effect of each charge on the VFB condition depends on its distance from the oxide/silicon interface and can be calculated from Gauss law. Assuming a uniformly distributed charge per unit volume, VFB shift induced by bulk charges will then vary with the square of its thickness (or EOT)
[2]. VFB shift induced by interfacial fixed charges results in a linear modification of the VFB vs EOT plot for a given oxide.
It has been experimentally demonstrated that VFB vs EOT plot is described by a straight line for SiO2 and HfO2 oxides [2] [5] [6]. Therefore, the impact of bulk charges in the dielectric layers is negligible. Moreover, recent studies have evidenced the independence of VFB shift with HfO2 thickness, implying that no isolated fixed charges are present at the HfO2/SiO2 interface or in HfO2 bulk. Indeed, any charge at HfO2/SiO2 interface or in HfO2 bulk would lead to increasing VFB shift when HfO2 thickness increases [6]. Based on these results, the VFB equation including the charges at the Si/SiO2 interface (QSi/SiO2) can be written as [5]: VFB = M − Si – QSi/SiO2 (EOT/ εsio2) 1.10
As the threshold voltage is related to the VFB, charges also directly influence the threshold voltage and most of the performance parameters of MOSFET devices, such as effective mobility, junction leakage, noise, reliability and breakdown voltage in discrete transistors and digital integrated circuits.
Dipole effect
Interface dipoles can be present in the gate stack at the various interfaces, where they generate potential drops (δ) and so their effect on VFB is independent of the thickness of the oxides. Several models have therefore been proposed to explain dipoles at various locations in the gate stack, in particular at metal/high-k interface and at high-k/SiO2interface. Dipole formation at the interfaces have been mainly explained by these two phenomena
• Electronegativity differences: Two materials in contact with each other will have atoms with different electronegativities at their interface. For instance at the interface between SiO2 and high-k, an atom of oxygen is bonded to an atom of high-k on one side and to an atom of Si on the other. Each bond has a dipole moment μ, which depends on the charge Q carried by the bond and its length d. In bulk high-k or SiO2, the dipole moments compensate each other, but at the interface a net dipole moment is created, which is the sum of individual dipole moments. HfO2 or La2O3 thus creates a dipole in contact with SiO2 (Figure 1.6). This mechanism has been utilized to explain VFB shifts due to dipole at many interfaces. Such as the dipole at the interface between metal gate and high-k dielectrics [7] [8], and also for the case of capping the top surface of the high-k layer with additives such as aluminum [9] or lanthanum [10].
Figure 1.6 Dipole moments associated with HKMG stack interfaces [11][12]
• Oxygen vacancy formation: According to this model, difference of oxygen atomic density (σ) at the interface causes deformation and strain at the interface, leading to an increase of free energy of the interface. The free energy of the interface should be therefore minimized by the movement of oxygen from larger σ side to the smaller [10]. As a result, a charge imbalance at the interface is induced by the movement of oxygen as it is negatively charged. This mechanism has been used to explain VFB shifts due to dipole at the metal/high-k interface [13] [14], at high-k/SiO2 interface [15] or at the Si/SiO2 interface [16].
The final equation of the VFB combining the effects of all the charges inside the gate stack and dipoles at the interfaces becomes: VFB = M − Si – QSi/SiO2 (EOT/ εsio2) + Σδ 1.11
VFB and EOT can be calculated by fitting experimental capacitance voltage curves. The above relationship between VFB and EOT can be used to extract gate stack charges and dipoles. QSi/SiO2 can be calculated from the slope of the VFB vs EOT curve and WFM + δ can be estimated from the extrapolated VFB value at EOT=0 [17]. Practically EOT is modulated along the wafer radius by varying the SiO2 IL, called as the bevel process (section 1.3.3) which has been developed at STMicroelectronics’s 300 mm wafer fab.
Metal effective work function
The work function of the metal WFM is defined as the minimum energy needed to remove an electron from the metal to a point in the vacuum immediately outside the metal surface. For an ideal device without any charges and dipoles, it is given as follows: WFM = q M = qVFB + q Si 1.12
We have seen that VFB of real devices can be affected by various process steps that can introduce fixed charges at the interface or in the bulk of oxides and interface dipoles. In this case, equation 1.12 does not hold any longer and the concept of effective work function WFeff has to be introduced. WFeff takes into account not only q M but also the VFB contribution of the charges and dipoles in the gate stack. So the WFeff is described as: WFeff/q = VFB + Si = M + ΔVFB, ΔVFB = – QSi/SiO2 (EOT/ εsio2) + Σδ 1.13
Gate stack fabrication process
Gate dielectrics
Gate dielectrics are responsible for the capacitive effect produced in a MOSFET device. Traditionally, SiO2 has been used as the gate dielectric, but continuous device scaling for future technology nodes required reduction in the thickness (or EOT) of gate dielectrics in order to maintain high drive current and adequate gate capacitance. This scaling of SiO2 was challenged due to exponential increase in gate leakage currents as the thickness decreased [18].
In order to replace SiO2 and to overcome these problems, SiO2 incorporated with nitrogen was proposed to form oxynitrides (SiOxNy). At the beginning this became an appropriate solution to increase MOSFET performance[19]. Compared to non-nitrided films, the oxynitrides films containing nitrogen atoms increased its diffusion barrier properties, leading them to be more resistant to further oxidation and diffusion of dopants from the gate to the channel and vice versa. Moreover, nitrogen atoms at the Si/SiO2 interface resulted in the reduction of defect generation and traps in the oxide [20]. In addition, nitrogen increases the dielectric constant of the oxynitride. This increase is linear with the percentage of nitrogen, from « SiO2 = 3.9 to « Si3N4 = 7.8 [21] and thus reduces gate leakage. SiON however reached its limits from the 45nm node because of the weak permittivity and degradation of reliability due to the presence of nitrogen atoms. Gate leakage on SiON dielectrics became superior to specifications recommended by the ITRS.
As an alternative to SiON gate dielectrics, a high permittivity (high-k) material was introduced to continue the aggressive scaling of advanced MOSFETs. Due to its high permittivity a larger thickness can be used, compared to SiON, while keeping the same EOT and thus decreasing the leakage current. The direct deposition of the high-k dielectric on the silicon substrate forms a layer of unintentional silica of poor quality and is detrimental to transistor electrical properties, such as threshold voltage, channel carrier mobility, interface traps and charges in the dielectric [22]. On the other hand, a well-controlled silicon oxide or oxynitride (SiO2, SiOx, SiON) (interfacial Layer (IL) deposited on Si substrate has excellent surface quality and therefore can reduce or even eliminate the above problems associated with a High-k/Si interface [23].
Interlayer dielectric growth
As mentioned above, the electrical properties of MOSFET devices are strongly correlated with structure and defects near and at the Si/SiO2 interface. High quality ultra-thin oxides films are not easily fabricated with conventional thermal oxidation methods. Therefore, enhanced techniques to grow ultra-thin SiO2 films with superior quality and performance have been designed and implemented in recent years. As discussed before, SiON has superior electrical properties compared to SiO2 and so we will focus on the deposition techniques for SiON.
The main fabrication techniques, used for SiO2 film growth, are the rapid thermal oxidation (RTO), in-situ steam generation (ISSG), rapid thermal chemical vapor deposition (RTCVD) and remote plasma enhanced chemical vapor deposition (RPECVD) [24]. Nitridation of SiO2 films, formed by RTO or ISSG, by DPN (decoupled plasma nitridation) or RPN (remote plasma nitridation) have been investigated earlier [24]. Nevertheless, nitridation in amonia (NH3) is a simple way to introduce relatively high concentrations of nitrogen into SiO2. The ultra-thin oxynitride (SiON) films (between 8Å and 12 Å), used in this work as the interlayer dielectric, is fabricated at STMicroelectronics by performing first an enhanced ISSG oxidation of silicon at 800°C, followed by NH3 nitridation and RTP anneal at 700°C.
High-k deposition
The SiO2 or SiON dielectrics by themselves are not able to satisfy the gate leakage requirements at the 45 nm node and beyond. The high-k material has to meet several criteria to be considered as
a candidate to replace SiO2, as listed below. The high-k must:
• Have a high enough dielectric constant
• Have a large conduction and valence band offsets relative to metal Fermi level and to the conduction and valence bands of silicon, as gate leakage decreases with band offsets.
• Form a good quality interface with the channel so as not to degrade mobility
• Have good stability in the different stages of transistor fabrication, meaning retention of the amorphous phase at high temperatures. Indeed, a polycrystalline material could result in grain boundaries acting as current leakage paths.
• Have minimum traps and fixed charges
• Meet the feasibility criteria in industrial conditions (thin layers, short deposit times, low thermal budgets and cost)
• Meet the requirements in terms of reliability
Among the various potential candidates, Hafnium-based dielectrics (HfO2 and HfSiOx silicates, HfSiON) best meet these criteria [24]. Within the International Semiconductor Development Alliance (ISDA), which included STMicroelectronics and IBM, HfSiON material was selected to succeed SiON in the technological nodes 32 / 28nm. Indeed, HfSiO silicates have better results than HfO2, because of better thermal stability, a gain in mobility and a reduction in charge trapping. However, it has been reported that HfO2 has a higher dielectric constant, about 18-25 [25], compared to about 15 for HfSiO [26]. Moreover, Hf-based gate dielectrics have high band offsets, Ec = 1.5 eV and Ev = 3 eV [25], leading to leakage current densities at least two orders of magnitude lower than SiO2. The presence of nitrogen in the film (HfON or HfSiON) enhances the thermal stability relative to HfSiO, leading to amorphous films up to annealing temperatures of 1100°C [27]. This high thermal stability makes these dielectrics suitable for integration into the CMOS process flow, being able to handle the subsequent source and drain high temperature anneals.
Initially, physical vapor deposition (PVD) was used to deposit hafnium-based gate dielectrics [27]. Now, chemical vapor deposition (CVD) or Metal organic CVD (MO-CVD) and atomic layer deposition (ALD) are being used to deposit these layers. This has been done to meet the compositional control and conformality requirements of the films. The CVD or MO-CVD processes, used to deposit HfSiO films, uses metal organic precursors. ALD processes are used to deposit HfO2 uses hafnium tetrachloride (HfCl4) as precursor. Finally, in order to incorporate nitrogen into the films to further increase the dielectric constant, nitridation methods such as Decoupled Plasma Nitridation are currently used. In 14 or 28 nm MOSFET devices fabricated at STMicroelectronics, HfON and HfSiON are deposited over the interlayer dielectric (SiON) by ALD or by MO-CVD respectively in order to keep a high mobility interface, followed by nitridation using DPN and Post-Nitridation Anneal before metal gate deposition. The resulting high-k layer has a thickness between 19Å and 21 Å.
Metal gate electrode and deposition techniques
Choice of gate material
Poly-crystalline silicon (poly-Si) has been used for decades as the gate for MOSFET. It was used for its good electrical conduction properties when doped with impurities. However, poly-Si could not be used for advanced technological nodes and metal gates were introduced for several reasons mentioned below:
• Metal gates eliminate the depletion zone formed at the poly-Si and high-k interface that acts as a parasitic capacitance, and boron penetration effects. This thus reduces the EOT penalty and increases the ON current of the transistors.
• Poly-Si in contact with high-k causes the Fermi level pinning. This causes the modification of the Poly-Si Fermi level due the formation of dipole at the poly-Si and high-k interface [13].
• Surface phonon scattering degrades the electron mobility in the high-k, reducing the speed at which transistors can switch. Introduction of metal gate significantly increases the density of electrons in the gate electrode [28]. Therefore, the higher density of electrons in a metal screen out the vibrations and let current to flow more smoothly, compared to poly-Si gate with lower free electron concentration.
• Metal gates show less resistance compared to Poly-Si gate.
Choice of Metal gate
The first criteria for the choice of metal gate is its work function WFm that determines the threshold voltage of the transistor. Advanced technology nodes requires low threshold voltage for both NFET and PFET devices. The effective work function target depends on the channel doping density [29] (Figure 1.7), as predicted by the term Nsc in Eq. 1.5. According to this, for high doping concentration, metals with workfunction close to the silicon conduction band (CB) or the silicon valence band (VB) are required, for NFETs and PFETs respectively [30]. In contrast, for low doping concentration, the target is almost midgap work functions, like TiN, at only 100 meV from either side of the intrinsic silicon Fermi level. Therefore, in fully depleted silicon on insulator (FD-SOI) devices with undoped Si channel, almost midgap metals will be required for low VT, in contrast to bulk technologies [31] [32].
Figure 1.7: Metal work function requirements as a function of channel doping density, to achieve low VT for both NFET and PFET devices [29]
The second criteria for the choice of the metal gate is its thermal stability. This means that their microstructure should remain stable and that they do not react with the other layers. During the process of MOSFETs devices, the development of HKMG stack is followed by a high temperature annealing (around 1050°C) for source and drain dopant activation (S-D anneal). This process method is termed as the Gate First approach. Figure 1.8 shows that only the mid-gap metals, including TiN, and high WFm metals are thermally stable above 700°C [33]. In contrast, low WFm metals, being less electronegative, will tend to form an oxide at high temperature.
Figure 1.8: Characteristics of metals in terms of thermal stability and workfunction, indicated by the gray level for the stability and an indication of N-like or P-like behavior index of each element [33]
Another effect of the high temperature annealing is the diffusion of oxygen from the metal gate towards the pedestal oxide and thus degrading the EOT of the device. This has been observed in particular for P type metals such as tungsten, platinum or rhenium but solubility of oxygen in pure titanium (Ti) is high (10%). In case of a Ti/HfO2/SiO2/Si stack, annealing even leads to the removal of some interfacial oxide [9]. This is due to the diffusion of oxygen from the pedestal SiO2, through the HfO2, toward the TiN gate due to the high solubility of oxygen in titanium nitride (TiN) and is called the oxygen scavenging effect. This strong affinity of TiN for oxygen makes it possible to reach EOTs of the order of 1 nm. All the advantages mentioned above (mid gap WFM, excellent thermal stability and the scavenging effect), makes TiN almost indispensable in a Gate First integration strategy.
Metal gate deposition techniques
TiN metal films are mainly deposited by Atomic Layer Deposition (ALD) and Physical Vapor Deposition (PVD) techniques. ALD is a thin film deposition technique that is based on the sequential use of a gas phase chemical process. ALD makes atomic scale deposition control possible and provides extremely conformal, uniform thickness and low impurity level films. It has successfully been used to deposit TiN films from TiCl4 and NH3 precursors [34]. However, despite these advantages TiN metal gate was not deposited by ALD in our work at STMicroelectronics. The main limitations of ALD were the slow deposition rate and high cost, which has limited its use in the semiconductor industry. However, ALD is becoming the preferred choice for applications that require high global thickness non-uniformity and conformal step coverage, such as for extremely scaled devices with gate last integration scheme. Nevertheless, for our work that uses the gate-first processes, such conformal step coverage is not essential. For this reason, Radio-Frequency PVD (RF-PVD), allowing deposition at room temperature and at higher deposition rates, have been chosen for metal gate applications at STMicroelectronics.
Physical Vapor Deposition
PVD processes include a variety of thin film deposition methods that are used to deposit thin films atomically by means of fluxes of individual neutral or ionized species. Cathodic arc deposition, electron beam physical deposition, evaporative deposition, pulsed laser deposition and sputter deposition are some examples of physical vapor deposition methods. In our work, TiN metal gate films has been deposited by the sputtering method.
Sputtering is the process of removing surface atoms or molecules from a solid target by the bombardment of ions and involves ejecting those atoms or molecules from a source (target) onto a substrate (silicon wafer). Sputtering, unlike evaporation, does not require melting the metal to be deposited. Therefore, refractory metals such as titanium (Ti) and tungsten (W), that are very difficult to melt, can be used. Sputtering also preserves the original composition of the target material. In addition, sputtering allows the deposition of many different materials by combining materials from solid and gaseous sources, which are introduced into the vacuum chamber either before or during deposition. This form of sputter deposition is called reactive sputter deposition.
The sputtering process is carried out in a vacuum chamber in order to avoid contaminants to interfere with the deposition process and to establish the pressure required by the sputtering plasma. The high vacuum pumping (in the 10-8 Torr range) is done by cryopumps. In a simple DC sputtering system, the target plays the role of the cathode and the substrate, that of the anode. When a DC voltage equal to a voltage known as breakdown voltage (Vb) is applied between both electrodes, a plasma is created. The electrons collide with argon and create positively charged argon ions (Ar+), which are strongly attracted to the negatively charged cathode (the target). The argon ions collide with the target surface and some of them causes surface atoms of the target to be ejected. The sputtered atoms travel to the substrate where they are deposited as a film.
For a given gas, the minimum voltage Vb necessary to create a stream of electron between the electrodes is a function of the product of the pressure (p) and the electrodes gap distance (d) (parameter pd in Fig. 1.9). The curve of voltage versus pd is called Paschen’s curve. Examples of Paschen’s curves obtained for different gases are shown in Fig. 1.9. The pressure has to be high enough to keep a high density of Ar+ ions in the plasma to sputter the target but low enough to reduce the collisions of the sputtered atoms with Ar atoms. A pressure too low or too high have to be compensated by higher breakdown voltages, as described in Figure 1.9.
Sputtering effects can be enhanced by adding magnets behind the cathode to a simple DC sputtering system. In this case, the sputtering rate is improved because the Ar ionization efficiency is enhanced. Electrons are confined because they tend to follow the magnetic field lines, ionizing more argon atoms in their path. In this way, both electron and Ar+ ions density are increased in a DC magnetron system. On one hand, with the increased electron density, Vb can be decreased from 5000 V – 10000 V in a simple DC sputtering system to only 400 V – 800 V in a DC magnetron system. On the other hand, due to the increased density of Ar+ ions, it is possible to lower the sputtering chamber pressure. At lower pressures, the sputtered atoms have fewer collisions on their path to the substrate which results in an increased deposition rate. Finally, the electron confinement in a magnetic field near the target also reduces electron bombardment of the substrate. This results in much less heating of the substrate.
In addition, a Radio Frequency (RF) generator operating at a frequency of 13.56 MHz (standard in industry) can be coupled to a DC power. The main interests of RF-PVD deposition are the reduction of the breakdown voltages and the improvement of film deposition uniformity. Indeed, the voltage needed to ignite the plasma is reduced because oscillating electrons are able to ionize more Ar gas. A direct consequence of the reduction of the breakdown voltage is that the metal atoms are ejected with less energy, limiting the damage that could be caused on the high-k layer by bombardment on the wafer during the plasma sputtering. This is a critical point because any significant damage can be detrimental for gate stack integrity and transistor electrical properties. In addition, less high energetic electrons are provided in a RF sputtering plasma compared to DC plasma for the same density of electrons, as shown in Figure 1.10.
Table of contents :
General introduction
Context
Thesis objectives and outline
1. Gate stack technology for 14/28 nm FDSOI MOSFET devices
1.1 MOSFET device
1.1.1 MOSFET operation
1.1.2 Metal-Oxide-Semiconductor gate stack properties
1.2 Gate stack fabrication process
1.2.1 Gate dielectrics
1.2.2 Metal gate electrode and deposition techniques
1.2.3 Metal gate integration in 14 nm Fully-Depleted SOI devices
1.2.4 Introduction of additives for workfunction engineering
1.3 Process flow
1.3.1 MOS transistor Process flow
1.3.2 Process flow simplification for MOS capacitor
1.3.3 Beveled Interlayer Oxide
1.4 MGG induced VT variability
1.5 MOSFET reliability
1.5.1 Bias temperature instability (BTI)
1.5.2 Time dependent oxide breakdown (TDDB)
1.6 Conclusion
2. Characterization techniques for the gate stack
2.1 Electrical characterization
2.1.1 CV measurements and electrical parameters extraction
2.1.2 Sheet resistance measurements by four probe method
2.2 Physicochemical and Stress characterization
2.2.1 X-ray Photoelectron Spectroscopy (XPS)
2.2.2 X-Ray Fluorescence (XRF)
2.2.3 X-Ray Diffraction (XRD)
2.2.4 Mechanical stress measurements
2.3 Conclusion
3. Impact of La and Al additives on MOSFET reliability
3.1 Impact of La and Al additives on BTI reliability
3.1.1 Device fabrication
3.1.2 Electrical measurements and analysis
3.1.3 Results
3.2 Impact of La and Al additives on TDDB reliability
3.2.1 Electrical measurements
3.2.2 Results
3.3 Conclusion
4. Impact of TiN process on its microstructure and electrical properties
4.1 Context
4.2 Device fabrication
4.3 Measurements and results
4.3.1 In-plane XRD for TiN grain size
4.3.2 θ-2θ XRD for TiN grain orientation
4.3.3 Mechanical stress
4.3.4 Resistivity of TiN films
4.3.5 Effective workfunction measurements
4.3.6 Grain size variation with wafer radius
4.3.7 Effect of substrate temperature
4.3.8 TiN grain analysis by ASTAR technique
Conclusion
5. Study of La and Al diffusion in HKMG stack
5.1 Introduction to diffusion
5.2 Device fabrication
5.3 Results
5.3.1 Modulation of diffused additive dose by DIA conditions
5.3.2 Modulation of effective workfunction by DIA conditions
Conclusion
6. X-ray Photoelectron Spectroscopy under bias
6.1 State of the art and the need for XPS under bias
6.2 Test structures and their biasing issues
6.2.1 Test structures and their process flow
6.2.2 Biasing issues in the test structures
6.2.3 Biasing solutions and electrical modelling
6.3 Issues related to the XPS equipment
6.3.1 Device location
6.3.2 XPS beam position error and size estimation
6.3.3 Impact of X-ray beam on the gate stack
6.3.4 Reduction of substrate resistance
6.4 XPS under bias technique validation
6.4.1 XPS spectra fitting methodology
6.4.2 Shift of binding energies with bias
6.4.3 Technique validation
6.5 Dipole localization by XPS under bias
6.5.1 Dipoles related to La and Al addition
6.5.2 Methodology to reduce experimental difficulties
6.2.3 Dipoles related to TiN thickness modulation
Conclusion
Conclusions and perspectives
List of publications
List of Patents
Annex
