DIGITAL AND MIXED SUB-SYSTEMS DESIGN

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Background to the research

Communication system engineers are often concerned with efficiency with which systems utilize signal energy and bandwidth. In most communication systems these are essential issues. However, in some cases, there exist situations in which it is necessary for the system to resist external interference, to operate at low spectral energy, to provide multiple access capability without external control, and to provide a secure channel inaccessible to outside listeners [1]. Thus, it is sometimes necessary to trade-off efficiency of a system for such enhanced features. Communication systems deploy spread spectrum techniques to achieve such features [2]. The theoretical aspects of using spread spectrum in a strong interference environment have been known for over four decades. It is only over the last decade that practical implementations became more feasible. Initially, spread spectrum techniques were developed for military purposes [3] and their implementations were exceedingly expensive. Technological advancements such as VLSI, and advanced signal processing techniques made it possible to develop cheaper spread spectrum equipment for general public use [4]. Applications of this technology include mobile phones, wireless data transmission and satellite communications .

Direct sequence spread spectrum (DSSS)

DSSS, also known as direct sequence code division multiple access (DS-CDMA), is one of two approaches to spread spectrum modulation for digital signal transmission over the airwaves. The design of a DSSS system introduces a set of trade-offs. Parameters such as power, bit error rate (BER), bandwidth, security and other related factors must be traded-off in order to find an optimal solution [19]. Under the DSSS scheme, each bit in the original signal is represented by multiple bits (chipping code) in the transmitted signal. The chipping code spreads the signal across a wider frequency band in direct proportion to the number of bits used [15]. The chipping code is a redundant bit pattern for each transmitted bit, thereby increasing the resistance of the signal to interference and corruption. The original data can be recovered if a number of bits in the pattern are damaged during transmission. A longer chipping code supports more users and provides for greater security, but this is at the expense of increased bandwidth [16], as well as time to establish correlation at the receiver. This in turn decreases the efficiency with which the data is received, and should be compensated for. The PN sequence used in DSSS systems should have good cross-correlation so as to support a multi-user environment, as well as good autocorrelation to allow for easy code synchronization. Various types of sequences, such as Kasami sequences and Gold sequences, are available for use in DSSS applications. However, trade-offs must be made once again when selecting the family of sequences. For instance, Gold codes provide a large number of codes, whilst introducing relatively high noise levels. As a rule of thumb only approximately 10% of the family size can be used whereafter the multi-user interference (MUI) would have grown to such proportions so as to render the processing gain useless [9]. Kasami sequences on the other hand introduce lower noise levels, but smaller family size. For this thesis, CSS is chosen. While CSS was proposed in 1992 [20], its usage in DSSS systems is proposed in the patent [12] for DSSS communication systems. The use of the CSS allows for various data rates by choosing different sequence lengths and transmission bandwidths. It also allows for a choice of modulation techniques and guarantees the processing gain of 20 dB. When CSS are used, a transmitter can operate in both balanced and unbalanced fashion by using one spreading sequence for every two-dimensions utilised.

System Analysis

The system analysis depends on the type of modulation scheme. Two techniques were considered, BPSK and Q2 PSK. Section 2.2.1 presents the BPSK based system analysis, which also serves to give a general system analysis, and then section 2.2.2 presents QPSK based system analysis. Furthermore, in Section 2.2.1 Gold codes of length 31 chips per data bit were chosen for the first analysis as they are easier to implement, and yield a CDMA system comparable with existing binary standards, which may also simultaneously provide some useful benchmark to compare with the CSS used in Section 2.2.2.

System inputs

Figure 2.17 shows the overall inputs and outputs of the system. The inputs to the system consist of the data signal inputs and the sequence inputs. The primary input to the transmitter (FU1) is a binary data signal running at a bit rate proportional to the RF transmission bandwidth divided by the CSS length. The secondary input to the transmitter (FU1) is a CSS of the chosen length. In order to transmit data at a high rate the sequence length should be as small as possible, but in order to keep the quality of the transmission the sequence should not be shorter than a certain length. The sequence length of 11 is used as the lower boundary to satisfy both conditions. The CSS used are the families of the GCL sequences. These sequences are the intellectual property of the University of Pretoria [8]. The primary input to the receiver is the noise corrupted transmitted signal (FU4) running at the rate of 20 Mchips/s, which corresponds to the bandwidth of 20 MHz. Complex spreading sequences form the secondary input to the receiver at FU5.

CMOS process parameters

The CMOS process used for this thesis is the AMS 0.35 μm process [28]. The C35B4C3 process allows for a minimum gate length of 0.35 μm, and has four metal layers and two layers of poly. A cross section of the wafer, shown in Figure 3.1 highlights the available layers and illustrates the layout of the transistor and capacitor modules. The process allows for n-channel MOSFETs (NMOS), p-channel MOSFETs (PMOS), resistors, capacitors, diodes and Zener diodes. Although the process does allow for BiCMOS fabrication1 it is more expensive to produce, for this reason this thesis is limited to MOSFET implementation.

TABLE OF CONTENTS :

• 1 INTRODUCTION
  • 1.1 Background to the research
  • 1.2 Justification for research
  • 1.3 Methodology
  • 1.4 Outline of this thesis
  • 1.5 List of publications
• 2 SYSTEM ANALYSIS AND DESIGN
  • 2.1 Direct sequence spread spectrum (DSSS)
  • 2.2 System analysis
  • 2.2.1 BPSK based system analysis
  • 2.2.2 QPSK based system analysis
  • 2.3 Developing the system specifications
  • 2.3.1 System inputs
  • 2.3.2 System outputs
  • 2.3.3 Major subsystem specifications
  • 2.4 System level simulation
  • 2.4.1 BPSK based system modelling and simulation
  • 2.4.2 QPSK based system modelling and simulation
• 3 ANALOGUE SUB-SYSTEMS DESIGN
  • 3.1 CMOS process parameters
  • 3.2 MOSFET summary
  • 3.3 Bias network design
  • 3.4 Amplifier design
  • 3.5 Mixer design
  • 3.6 LNA design
  • 3.7 Active Inductor design
  • 3.8 Integrate and dump
  • 3.9 Comparator
  • 3.10 Phase detector
  • 3.11 Summing circuit
  • 3.12 High-frequency buffer
  • 3.13 Filter design
  • 3.14 Sequence processing circuit
  • 3.15 Power amplifier
• CHAPTER 4: DIGITAL AND MIXED SUB-SYSTEMS DESIGN
  • 4.1 Digital sub-systems
  • 4.1.1 Bidirectional transmission gate
  • 4.1.2 Logic gate – inverter
  • 4.1.3 Logic gate – NAND
  • 4.1.4 Logic gate – NOR
  • 4.1.5 D-Type flip-flop (FF)
  • 4.1.6 Counter
  • 4.1.7 Parallel-to-serial (P/S) converter
  • 4.1.8 Serial-to-parallel (S/P) converter
  • 4.1.9 Clock recovery
  • 4.1.10 Error correction
  • 4.2 Mixed circuit sub-systems
  • 4.2.1 Sequence mixer
  • 4.2.2 Digital buffer
• CHAPTER 5: SYSTEM INTEGRATION
  • 5.1 Simulation results for the integrated system
  • 5.2 Qualification test protocol
  • 5.2.1 Carrier frequency of the transmitted signal
  • 5.2.2 Transmitted bandwidth
  • 5.2.3 Transmitter power
  • 5.2.4 Receiver sensitivity
  • 5.2.5 Bit error rate test
  • 5.2.6 CDLL BER
  • 5.2.7 Power dissipation
  • 5.3 Prototyping of design
  • 5.3.1 Design submission to Europractice
  • 5.3.2 Packaging & test printed circuit board (PCB)
  • 5.3.3 High-frequency equipment and test-bench
  • 5.4 Practical measurements
• CHAPTER 6: CONCLUSION
  • 6.1 Technical summary and contribution
  • 6.2 Future research work
  • REFERENCES
  • APPENDIX A: OP-AMP DESIGN
  • APPENDIX B: CHIP PHOTOGRAPHS

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A MULTI-DIMENSIONAL SPREAD SPECTRUM TRANSCEIVER