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Operation Principle
The operation principle of all 1T-DRAM versions, illustrated in Figure 1.29, is almost the same. The state “1” reflects an excess of majority carriers in the body causing an increase of the potential (VB > 0 V) and drain current while the “0” state consists of removing majority carriers from the body. In this case, the potential is lower implying higher threshold voltage Vth and low drain current.
Figure 1.29. ID-VG transfer characteristics of N-channel SOI MOSFET transistor showing the 1T-DRAM memory « 1 » and « 0 » states.
In order to generate the majority carriers, several mechanisms have been offered such as impact ionization, bipolar junction transistor, and band-to-band tunneling. The Table 1.1 presents the impact ionization technique used to program the state “1” of 1T-DRAM in both Bulk and PDSOI technologies. Erasing, reading and holding methods are also mentioned.
The operating mechanisms are almost the same in these technologies. However, they differentiate in holding the stored information. In order to limit the leakage current and save the information for a long time, in PDSOI technology, the front gate is biased negatively keeping the diodes in reverse mode. Programming state “1” is done by impact ionization. A positive voltage pulse is applied on the front gate (VGf > Vth) accompanied with a positive drain pulse higher than the saturation voltage VDSAT. With these polarizations, the electrons in the channel are accelerated by the high electric field present in the space charge region close to the drain and generate by impact ionization electron-holes pairs. The electrons are guided towards the drain while holes are injected into the floating body of the transistor where they will be stored. For the “0” state, the drain/body junction is forward biased by applying a negative drain pulse. In this case, the stored holes are evacuated and electrons are injected from the drain into the body lowering the potential. At the same time, in 1T-Bulk devices, a negative pulse is applied on the front gate switching off the transistor and strongly reducing the dynamic power consumption. In order to keep a remarkable margin between “0” and “1” states, it is strongly recommended in PDSOI technology to bias positively the gate instead of a negative pulse. Although, a negative gate pulse is used for “0” selective writing mode which is a big challenge in 1T-DRAM world. In reading mode, a high positive pulse is applied on the front gate terminal, while the drain voltage is smaller (< VDSAT) in order to not trigger the impact ionization mechanism that will disturb the “0” state of the memory cell. During all memory operations, the N buried layer (in Bulk technology) should be biased positively allowing a perfect body isolation. In this case, the leakage current of the reversely biased P-N diode is low.
This overview allows us to conclude that DRAM architectures without external storage capacitor in bulk technology can be used for embedded memory applications while PDSOI devices are viable as standalone memories. However, the evolution of 1T-PDSOI memory cells is facing serious problems with CMOS downscaling. In order to guarantee the neutral zone in sub-100 nm node, the channel doping concentration is increased. This high doping level induces threshold voltage variation and the generation current increase at the source/drain terminals affects the “0” retention time. On the other hand, 1T-Bulk memories seem to be compatible with eDRAM applications until 45 nm node according to ITRS 2003. Beyond this node, innovative solutions are needed to ensure the 1T-DRAM concept continuity. In the following, we describe the benefits of 1T-DRAM devices in Fully Depleted SOI (FDSOI) technology and how they operate.
T-DRAM in Fully Depleted Silicon on Insulator (FDSOI) Technology
Motivations
Short-channel effects (SCE) appear in Bulk and PD devices when they are scaled down beyond 45 nm node which affects their operation as dynamic memories. In particular, the control of “0” state, especially in holding mode, becomes impossible. Doping the channel with high concentrations increases the leakage current of junctions [100] which affects the “0” state retention time. By way of explanation, previous technologies cannot ensure anymore the continuity of capacitor-less DRAM keeping a remarkable current margin and high retention time. For this purpose, developing innovative architectures with thin silicon film is a must. In fact, SOI transistors with Fully Depleted body (FDSOI) attract much attention due to their numerous advantages [101]: better electrostatic control, steeper subthreshold slope and higher saturation current. In this context, researchers and industrial companies decided to test FDSOI transistors with thin silicon film as 1T-DRAM, believing that one day they will be fully compatible with CMOS logic transistors fabrication. The operation principle of FDSOI transistors and the memory variants are investigated in the next paragraph.
Operation Principle and 1T-FDSOI Memory Variants
Compared to PDSOI dynamic memories, operating with one single front gate and grounded back gate, FDSOI devices need back-gate biasing to perform as 1T-DRAMs. In fact, the potential distribution in a thin silicon film is completely different from that in partially depleted body. The source/substrate barrier is high enough allowing the accumulation of holes in the substrate where the potential-well is quite deep. This barrier is reduced in FDSOI technology due to the strong coupling effect between the front and the back gates. Here, holes are evacuated into the source instead of being accumulated in the transistor body. Nonetheless, floating-body effects, in particular the Kink, appear again in FDSOI transistors when the back gate is negatively biased. Holes can accumulate in the silicon film inducing a front-channel threshold voltage reduction and drain current increase which is also the origin of Kink effect.
In 2004, first FDSOI memories without capacitance appear with two different silicon film thickness (16 nm by STMicroelectronics [102] and 55 nm by Toshiba [103]). Few years later, other variants such as double-gate 1T-DRAM, floating-junction gate devices and FinFet configurations have been developed. In the following, we present the most recent capacitor-less dynamic memories in FDSOI technology featuring interesting results in terms of current margin, retention time and integration density.
MSDRAM
MSDRAM is a single-transistor operating as capacitor-less DRAM [104]. The operation mechanism is based on Meta Stable Dip effect (MSD) discovered in 2004 [105]. This unusual floating body effect appears in regular FDSOI transistors where the double (front and back) gates cooperate by coupling, giving rise to a hysteresis in transfer ID-VG characteristics, illustrated in Figure 1.30-a. State “1” features at the same time a back inverted channel (VG2 > Vth2) and an accumulated front interface. It is programmed by applying a high negative front gate pulse (VG1P ~- 6 V) that triggers B2B tunneling and efficiently fills the front channel with holes. State “1” is revealed by a high current flow at the back channel. Programming “0” state is obtained by deep depletion of the device, achieved by applying a less negative front-gate pulse (starting from 0 V to VG1P ~ – 3 V). At this time, the device does not reach equilibrium (because there are no holes available) and the channel goes into deep depletion; hence the back channel current is temporarily suppressed. This method, called capacitive coupling (CC), exhibits better results than impact ionization or forward biased junction mode (FBJ). The current margin is enlarged and the retention time is improved, as shown in Figure 1.30-b. Another advantage of this cell is the low drain voltage in reading mode (VD ~ 0.1-0.2 V). Reading the memory state implies a moderate front-gate pulse (- 4 V < VG1R < – 2.3 V) leading to a long retention time.
Figure 1.30. (a) Drain current ID measurements for direct and reverse scan of front gate voltage (VG1) for VG2 = 30 V, VD = 0.1 V. (b) Compared conventional programming methods (Impact Ioniziation II vs B2B tunneling for state « 1 » and Capacitive Coupling CC vs Forward Biased drain Junction FBJ for “0” state) showing higher retention time and sensing margin I1-I0 for MSD methods (BTBT and CC) at 85°C. tBOX = 400 nm, LG = 1.5 µm.
2-D simulations showed that MSDRAM can be scaled down to 25-50 nm channel length with remarkable current margin and retention time at low front-gate voltage, as seen in Figure 1.31. Also, this memory cell can achieve a non-volatile function with replacing the positive back gate bias by a positive charge trapped in the BOX [106].
Figure 1.31. Two dimensions (2D) simulations for MSDRAM with 50 nm gate length, 40 nm silicon film thickness, 3 nm front oxide and 6 nm buried oxide. The retention time is 14 s for a marge of 1 decade between I1 and I0 at 25°C at low front gate voltage VG1 = – 1.5 V. Programming time TP = 5 ns.
The 1T-MSDRAM is simple to program and read. It features a good current margin and high retention time. However, the memory cell suffers from super-coupling when the silicon film thickness goes into values smaller than 10 nm [107]. In fact, the coexistence of two types of carriers in the channel at the same time is not possible anymore.
A-RAM Family
In order to suppress the super-coupling effect and be certain of the presence of two types of carriers in transistors with tSi < 10 nm, a new concept has been proposed in 2009 [108]. The Advanced RAM (ARAM) memory cell body, presented in Figure 1.32-a, is divided by a middle oxide (MOX) into two parts. The upper region is dedicated for storing majority carriers while electrons are present in the lower semi-body with the intention of current sensing. State “1” programming consists of filling the upper body part with holes using impact ionization or B2B tunneling techniques. The holes will enable, by electrostatic coupling through the MOX, an electron current flow in the sense region (lower semi-body). In contrast, when there is no charge stored above MOX, the concentration of minority carriers (electrons) in the bottom of the body is very low (due to full depletion) defining the state “0” with no current flow. Positive drain pulses are used to read the memory states. This memory cell exhibits decent retention time, low power operation and sufficient current margin. Also, with ONO stack for the MOX the Advanced RAM could present a nonvolatile functionality [109].
Table of contents :
Chapter 1. Sharp-Switching Devices: State of the Art and Applications
1.1. Introduction
1.2. MOSFET Transistor: State of Art and Trends
1.3. Migration to FDSOI
1.3.1. SOI Technology
1.3.2. MOS Transistor in UTBB FDSOI Technology
1.4. Sharp-Switching Devices
1.4.1. Tunnel Field Effect Transistor (TFET)
1.4.2. Ferroelectric FET
1.4.3. Nano-electro-mechanical FET
1.4.4. NEM Relay
1.4.5. I-MOS: Impact Ionization MOSFET
1.4.6. Band-Modulation Devices: Operation Principle and Variants
1.5. Electrostatic Discharge (ESD)
1.5.1. Context and Physical Mechanism
1.5.2. ESD-Induced Failure in Integrated Circuits
1.5.3. ESD Stress Models
1.5.4. Protection Methods
1.5.5. Characterization Methods
1.6. 1T-DRAM: Capacitorless Dynamic Random Access Memory
1.6.1. Introduction
1.6.2. Motivations and State of the Art
1.6.3. 1T-DRAM in Partially Depleted SOI and Bulk Technologies
1.6.4. 1T-DRAM in Fully Depleted Silicon on Insulator (FDSOI) Technology
1.7. Conclusion
1.8. References
Chapter 2. Band-Modulation Devices: Fabrication Process and Operation Principle
2.1. Introduction
2.2. Zero Subthreshold Slope and Zero Impact Ionization FET: Standard Z2-FET
2.2.1. Device Fabrication
2.2.2. Principle of Operation
2.3. Novel Band-Modulation Device with Dual Ground Planes: Z2-FET DGP
2.3.1. Device Architecture
2.3.2. Advantage of Dual GP
2.4. Back-Gate Modulated Device with No Front-Gate : Z3-FET
2.4.1. Fabrication Process
2.4.2. Advantage of No Front-Gate
2.5. Conclusion
2.6. References
Chapter 3. Measurement and Modeling of Z-FET Family Devices
3.1. Introduction
3.2. DC Measurements
3.2.1. Impact of Silicon Thickness on Z-FET Devices Behavior
3.2.2. Impact of Z-FET Devices Parameters
3.2.3. FDSOI 28 nm node vs. 14 nm node
3.3. TLP Measurements
3.3.1. Standard Z2-FET
3.3.2. Z3-FET
3.3.3. Stacked Architectures
3.4. Interface Potential Analytical Model
3.4.1. Introduction
3.4.2. Potential Distribution Model
3.4.3. Model Verification
3.4.4. Z2-FET DGP and Z3-FET
3.5. Conclusion
3.6. References
Chapter 4. Z-FET Devices as 1T-DRAM and Logic Switch
4.1. Introduction
4.2. Capacitor-less Dynamic Random Access Memory: 1T-DRAM Application
4.2.1. Operation Principle
4.2.2. Memory Operation Analysis via TCAD Simulation
4.2.3. Measurement Bench
4.2.4. Transient Experimental Results
4.2.5. Z2-FET Memory Cell in a Matrix
4.3. Z2-FET DGP as a Logic Switch in 14 nm node
4.3.1. Transient Experimental Results
4.4. Conclusion
4.5. References
Conclusion and Perspectives
