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We have seen that the performance of existing wake-up receivers does not match that of standard data receivers for either the 802.15.1 or 802.15.4 standard. Performance areas which can be targeted for improvement include but are not limited to interferer robustness and multi-channel capabilities. As a solution to this we have proposed the use of an IF filtering stage based on a CT-ADC-DSP which, thanks to its highly tunable transfer function, enables the separation of the useful signal from excess noise and interferers.
The proposed stage is compatible with most existing WU-RX implementations, however, for completeness, we have also proposed a new WU-RX architecture which has a scalable performance – power trade-off. This architecture has only been studied at a system level in order to define a set of specifications for the proposed IF filter (summarized in Table 1.4); its implementation is beyond the scope of this manuscript and is not discussed in any of the following chapters.
Continuous Time Processing Chain
Their principle of operation as well as critical system-level trade-offs for minimizing the power consumption are highlighted and analyzed. In the second part of this chapter, based on previously derived system-level specifications, we estimate the power consumption of our system, by extrapolating state of the art CT-ADC-DSP implemen-tations. We show that the reuse of concepts from existing systems results in a power consumption well beyond the 100µW budget of our implementation. Consequently, in the last part of this chapter we present a new CT-ADC architecture designed to greatly reduce the power requirements of the subsequent CT-DSP. This architecture is particularly adapted for efficiently processing IF signals in the back-end of low power radios where signals are characterized by having a high likelihood of containing strong, out-of-band components which need to be removed for successful demodulation.
Classification of the Different Signal Processing Do-mains
According to the discrete / continuous nature of the time and amplitude of signals, we can distinguish four signal processing domains, as shown in Figure 2.1:
• Continuous in Amplitude and Time: The circuits which fall in this category are usually build around operational transconductance amplifiers (OTAs) or Gm − C cells. These truly analog systems have been widely studied from the beginning years of microelectronics and even in the beginning years of electronics.
• Continuous in Amplitude and Discrete in Time: For this class of systems the signal is defined as having an arbitrary value at specific moments in time, usually defined as multiples of a master clock. An example of such systems are switched capacitor circuits (in which case the signal is defined as the charge moving from and to capacitors).
• Discrete in Amplitude and Time: Classic digital signal processors fall in this category. The signal is quantized by an ADC which associates a discrete binary word to the analog signal presented at its input at time instants defined by the sampling clock.
• Discrete in Amplitude and Continuous in Time: Such an operation mode is obtained by removing the clocks from the previously described class of systems.
For this manuscript we focus on the implementation of a system falling in the last category. The reasons behind this choice are mainly related to the specific requirements of our application: a high degree of programmability for a very low power consumption. It will be seen in the following sections that CT-ADC/DSP systems are very good candidates for achieving such goals.
Description of the CT-DSP Chain
A CT-DSP chain can be divided in two parts: one for the CT analog-to-digital conversion and the other containing the CT digital signal processor unit.
CT-ADC
The role of a CT-ADC is to convert the input analog signal into a signal which is discrete in amplitude and continuous in time.
Operation Principle
Like sampled ADCs, there exist several CT-ADC architectures which can be differentiated based on their principle of operation as well as on the encoding of the data at their output. So far, two CT-ADC architectures have been proposed in literature: the flash CT-ADC [37], [40] and the delta-modulator CT-ADC [41], [42], [43], [44], [45], [46], [47], [48]. For the purpose of this introduction, the operation principle of the flash CT-ADC is analyzed, however, the conclusions based on this analysis apply to all CT-ADCs presented in the literature so far.
The basic operation of a flash CT-ADC is presented in Figure 2.2: a series of discrete quantization levels are defined and assigned to a digital word ranging from 0 to the full scale of the ADC. The input, analog signal, is compared to each of these levels using a bank of continuous time (non clocked) comparators. Whenever one of these levels is crossed by the input signal, the corresponding comparator triggers its output. This change is reflected in the digital output word through a decoder (in this case a thermometer to binary decoder is required). This digital output is fed to the CT-DSP as the digital representation of the signal at the input.
The previously described system has the interesting property of automatically scaling its power consumption according to the input signal properties [36]. The ideal configuration for such a system is achieved when the input is sparse in the time domain, i.e. it contains long periods when the input is constant. The power consumption of a CT-ADC quantizing such a signal is portrayed in Figure 2.4. When the input is constant, no comparators are triggered, hence no dynamic power is drawn. The power consumption of the CT-ADC thus becomes equal to the static power consumption of its building blocks which can be very low. As the input signal starts to evolve more rapidly (i.e. its first derivative is large), the frequency of events at the output of the CT-ADC also increases thereby increasing its dynamic power consumption.
We can thus conclude that, in terms of power consumption, the CT-ADC performs favorably when quantizing signals with long periods of “silence”. According to the Nyquist criterion, the sampled ADC is required to sample at a frequency greater than twice the highest frequency expected at the input, even when the signal to be quantized is constant. On the other hand, this advantage is lost for time varying input signals such as pure sinusoids: Nyquist ADCs require two samples per period while CT-ADCs can trigger all of their quantization levels (if the input is full-scale) over one period. This increases activity at the output of the CT-ADC which translates into an increased power consumption of both the CT-ADC and of the CT-DSP. Consequently, it may seem tempting to reduce the number of quantization levels of a CT-ADC in order to optimize its power consumption; unfortunately, this comes at a cost as its linearity also degrades. This trade-off occupies a central role in CT-ADC design and is discussed next.
Linearity – Activity Trade-Off
For a mid thread quantizer with a step of Δ and a total number of levels, N, as defined in the Figure 2.3, it can be proven that a single tone input (Vin(t)) of frequency f yields an output q(t) which can be decomposed in a Fourier series (c(n)), as given by equation 2.2 – equation 2.4 ([39] and [49]). Thus we can conclude that, in the frequency domain, the signal at the output of an ideal CT-ADC contains only the input tone, its odd order harmonics and no quantization noise in-between. These spectral properties have been derived and experimentally proven in [50]. For more mathematical properties of continuous time digital signals, the interested reader can refer to [51], [52], [53], [54].
Table of contents :
1 Introduction: Wake-Up Radios
1.1 Power Considerations in Wireless Sensor Networks
1.2 Wake-Up Receivers State of the Art
1.2.1 Architecture Considerations
1.2.2 Performance Analysis of Existing WU-RXs
1.3 Proposed WU-RX architecture
1.3.1 Proposed System
1.3.2 Low Power – Low Sensitivity WU-RX
1.3.3 High Sensitivity WU-RX
1.3.4 Interferer Resilient WU-RX
1.4 Tunable Filter Design
1.4.1 Continuous Time Analog Domain Filters
1.4.2 Discrete Time Charge Domain Filters
1.4.3 Digital Signal Processing
1.4.4 Continuous Time Digital Signal Processing
1.4.5 Tunable Filter Choice
1.5 Study of the Proposed CT Filtering Architecture
1.5.1 Single Tone Reception
1.5.2 Single Tone Reception with an Interferer
1.5.3 Single Tone Reception with Two Interferers
1.6 Wake-Up Receiver Design Conclusions
2 Continuous Time Processing Chain
2.1 Classification of the Different Signal Processing Domains
2.2 Description of the CT-DSP Chain
2.2.1 CT-ADC
2.2.2 CT-DSP
2.3 Co-Designing the CT-ADC with the CT-DSP
2.4 Proposed CT-ADC Architecture
2.4.1 Filtering CT-ADC Principle
2.4.2 Reducing the Input Event Rate
2.4.3 Effects on the Linearity of the Conversion
2.5 CT-ADC/DSP Conclusion
3 Energy Efficient CT-ADC
3.1 Previous Work
3.1.1 Basic Architectures
3.1.2 Improved Delta-Modulator Based CT-ADCs
3.2 Proposed CT-ADC
3.2.1 Improved Commutation Scheme
3.2.2 Proposed Architecture
3.2.3 Features
3.2.4 Possible Errors
3.3 Transistor-Level Implementation
3.3.1 Comparators
3.3.2 Transconductance
3.3.3 Threshold Management
3.3.4 Breakdown of the CT-ADC Power Consumption
3.4 Measurement Results
3.4.1 Single Tone Input: Noise
3.4.2 Two Tone Input: Linearity
3.5 CT-ADC Conclusion
4 Power Scalable CT-DSP
4.1 CT-DSP Architecture
4.1.1 Dual FIR – IIR Implementation
4.1.2 CT Digital Filter Design
4.1.3 Architecture Simulation
4.1.4 CT-DSP Specifications
4.2 CT Delay Cell
4.2.1 State of the Art for Asynchronous Delay Cells
4.2.2 Delay Cell Design
4.2.3 Delay Cell Architecture
4.2.4 Calibration and Matching
4.2.5 Delay Architecture Summary
4.3 CT Adder
4.3.1 Previous Work
4.3.2 Proposed Weighted-CT-Adder
4.3.3 Adder Performance
4.4 DF-CT-ADC
4.4.1 CT-ADC – CT-FIR Integration
4.4.2 Dispatcher
4.4.3 Voltage Gain and Filtering
4.4.4 Feedback Gm
4.5 Simulation/Measurements Results
4.5.1 DF-CT-ADC Performance
4.5.2 CT-FIR Performance
4.5.3 Interferer Rejection
4.5.4 Power Consumption Scaling
4.5.5 Noise
4.5.6 Comparison with State of the Art
4.6 CT-DSP Conclusion
5 Conclusion
5.1 Motivations and Contributions of this Work
5.2 Improvements of the Proposed Design
5.2.1 CT-ADC
5.2.2 DF-CT-ADC Feedback Path
5.2.3 CT-DSP Delay Cells
5.3 Future Work
