Digital transmitter architecture

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State-of-the-art in transmitter architectures

The state of the art presented in this subpart is a comprehensive, but not exhaustive, picture of digital transmission architectures at the beginning of this work in 2004. It depicts the general trends for implementing transmission architectures. Later work and results from other research teams will be discussed in the conclusion.
It will be shown that, following the evolution of transmission architectures, the global trend is to digitize the transmission chain. To visualize this trend, a color code has been employed on the different figures. All digital parts appear in green, whereas analog ones are in red. An intensity code is also used to separate baseband blocks (very light color) from RF parts (strong ones). IF processing blocks appear in an intermediate intensity. A cutting edge in RF transceiver architectures for WCDMA has been made in 2001 in [7].

Analog front-end architectures

Traditionally, transmitter architectures are almost exclusively analog in all front-end parts. Digital blocks are only found in baseband and digital-to-analog conversion is made with baseband DACs at low sample rates. Then, two implementations exist:
Most of the existing transmitters are based on a two-step up-conversion architecture (Figure 1-3), called heterodyne transmitter. An interesting implementation can be found in [8]. The signal is first up-converted to an intermediate frequency, filtered, up-converted to the radio frequency, amplified and finally filtered again before emission on the antenna. The filtering at IF or RF cannot be done with active structures, which makes it very difficult to completely integrate transmitters. Furthermore, two different local oscillator signals are needed.
Figure 1-3 Heterodyne transmitter architecture
An obvious solution would be to use only a direct up-conversion architecture, where the baseband signal is directly modulated to RF (Figure 1-4). However, the direct conversion or homodyne transmitter suffers from low performances at low output power and from a phenomenon called LO-pulling. The oscillator in the frequency synthesizer operates at the same frequency as the power amplifier in the transmitter. Due to the limited amount of isolation achievable, the transmitted output signal will couple to the oscillator and seriously degrade its performances. Moreover, the quadrature upconverter suffers from a higher IQ mismatch than in heterodyne transmitters, as it is now operating at RF. Examples of homodyne implementations can be found in [9].

Digital IF architectures

Figure 1-5 Digital-IF transmitter architecture
An evolution from previous implementations is the Digital-IF architecture, in which the digital signal is converted to analog after IF quadrature upconversion, generally using a Σ DAC (Figure 1-5). This architecture benefits from better silicon integration, ideal IQ matching and thus a lower error vector magnitude.
An interesting implementation is presented in [10] and [11], which details a digital quadrature modulator, associated with a 1-bit Σ modulator and a current-mode DAC to replace analog IF upconversion (Figure 1-6). The 0.13µm CMOS chip can work with a 700MHz clock frequency to address an IF frequency of 175MHz. It consumes 139mW at 1.5V and occupies 5.2mm².
Figure 1-6 Digital quadrature modulator from [10]
In [12], this kind of architecture is implemented using a second-order-hold DAC in 0.25µm SiGe BiCMOS (Figure 1-7). The multi-bit delt a-sigma DAC is working at 250MHz. Analog Variable Gain Amplifier (VGA) and mixer stages are integrated into the chip to deliver an output power of 5dBm, while consuming 180mW at 3V. However, this structure is working with current-mode DACs, which limits, at low voltage, the maximum power that can be delivered to a load. Such structures are incompatible with more efficient class-S power amplification.
Figure 1-7 Conceptual block diagram of the digital-IF heterodyne transmitter from [12]

Digital RF architectures

Figure 1-8 Digital RF transmitter chain
Advances and maturity of deep submicron CMOS technologies enable the DAC to reach higher sample rates. So, the idea of a digital RF implementation is rising [4, 5, 13] . It deletes all analog mixers and replaces them by a direct-digital quadrature upconverter and a switching-mode power amplifier driven by, e.g., a Σ -modulated high-speed signal (Figure 1-8 and Figure 1-9). An advantage is the high efficiency of the output stages. At the time of this work, no IC implementation of this kind of structures can be reported. However, ideas for such architectures are presented in several publications.
Figure 1-9 DSP-based wireless transmitter architecture from [5]
The fundamental concept is to use bandpass Σ modulation to produce a high-speed digital signal driving a switching PA:
• [14] demonstrates such a digital transmission chain by experimentally generating the produced bit-stream with a pattern generator and a serializer.
• [6, 15-17] present the concept and show simulation and measurement results for relatively low output frequency, extrapolating simulations to higher output frequencies.
Another method for digitally generating an RF signal is termed “Quadrature Integral Noise Shaping” (INS) and uses PWM coding scheme to generate baseband IQ complex signals. References [18] and [19] detail related architectures.
Moreover, an interesting paper [20] proposes to drive a DCO (Digitally Controlled Oscillator) with a Σ -modulated signal to generate the phase information and to regulate the power amplifier amplitude to control the amplitude information.
Digital generation of RF signals by Σ modulation and switched power amplifiers seems to be the most promising implementation in terms of configuration possibility and software radio convergence.

UMTS standard specifications

The Universal Mobile Telecommunications System (UMTS) in Frequency Division Duplex (FDD) mode will be first considered in order to emphasize the concept studied in this work. UMTS is the standard chosen for 3G mobile communications in Europe. Specifications for the UMTS standard are defined by ETSI [21]. These specifications cover all aspects of transmission and reception for handset terminals. As an introduction to UMTS, only aspects that concern the definition of the global transmitter to be designed are given hereafter. Furthermore, the extension of the highlighted approach to other standards is still under investigation and will be discussed in the conclusion.

Introduction to UMTS

Protocol layers

The architecture of the UMTS radio interface is structured into layers, in which protocols are based on the first three layers of the Open Systems Interconnection (OSI) reference model [22], as illustrated in Figure 1-10:
• The first layer is the physical one, devoted to transmit and receive data over the channel.
• The second layer is the medium access control (MAC), which is able to control the data sent and received and to retransmit error packets. This layer provides data and information to the physical layer.
• The third layer is the radio resource control (RRC). It controls and maps the connections.
Figure 1-10 Radio interface protocol structure [22]
In the following sections, only transmitter physical layer, starting from the baseband signals provided by the MAC layer will be considered.

 Access mode and frequency allocation

The frequency sharing technique adopted for UMTS is the Code Division Multiple Access (CDMA): data from different users coexist within the same channel and spread spectrum modulation is used to attribute a specific code to each user. Two methods allow spreading signals: the Frequency Hopping (FH-SS) technique and the Direct-Sequence one (DS-SS) [23]. Since only the DS-SS technique is adopted in UMTS, it is shortly detailed hereafter. Direct-Sequence spread spectrum consists in multiplying the signals symbols by a specific pseudo-random binary sequence. CDMA systems using direct sequence spreading are called DS-CDMA. For UMTS, information is spread over about 5MHz, hence it is called WCDMA (W is for Wideband). Two duplex modes exist in UMTS, Frequency Division Duplex (FDD) and Time Division Duplex (TDD).
Figure 1-11 gives a comparison between spectrum access techniques used in GSM and UMTS. For GSM, the whole frequency band is split into 200kHz wide channels multiplexed in time between emission and reception. For UMTS in TDD mode, information is spread over 5MHz channels and separated per code. The transmitter and the receiver are working in half-duplex. Time slots are alternatively allocated for emission and reception. FDD mode also uses CDMA but the transceiver is working in full-duplex. The reception band is placed away from the emission band (not shown in the figure). The two front-end architectures operate at the same time, using a duplexer.
Figure 1-11 Examples of access modes for GSM, UMTS TDD and FDD
The study is focused on FDD mode in which uplink and downlink are separated in two frequency bands, instead of separated time slots. UMTS FDD operates on two 60MHz bands, separated by 190MHz. The uplink uses 1920-1980MHz band while the downlink band is located between 2110 and 2170MHz. Our interest only goes to the uplink path, from the user terminal to the base station.
Inside the 1920-1980MHz band, twelve 5MHz wide channels exist. Chip rate is 3.84Mc/s (Mega chips/second), but data rate is tied to the spreading factor. Channels are larger than the relative chip rate due to the roll-off factor (generally stated α) of the Root-Raised Cosine (RRC) filter used. In UMTS, the roll-off factor is equal to 0.22, thus the channel bandwidth is equal to chip rate (1 ) 4.68MHz. A channel is shown on Figure 1-12, illustrating the effect of the root-raised cosine filter. The modulation used by UMTS is the Quaternary Phase Shift Keying (QPSK).

UMTS specifications for transmitters

Specifications on spectrum emissions are given at the antenna connector. It will be considered that the antenna connector is loaded by a nominal single ended 50 impedance. These specifications lead to a spectrum emission mask and out-of-band spurious emissions constraints as explained in the following sections.

Spectrum emission mask

The spectrum emission mask applies to frequencies, which are between 2.5 MHz and 12.5 MHz away from the User Equipment (UE) centre carrier frequency (related to the chosen channel). The out-of-channel emission is specified relative to the RRC filtered mean power of the UE carrier. Table 1-1 shows requirements for UMTS spectrum emission mask and Figure 1-13 translates the requirements on a graph.

Table of contents :

Introduction
Chapter 1 Background
1.1 Software defined radio
1.1.1 Universality of RF transmitters
1.1.2 Ideal software radio
1.2 State-of-the-art in transmitter architectures
1.2.1 Analog front-end architectures
1.2.2 Digital IF architectures
1.2.3 Digital RF architectures
1.3 UMTS standard specifications
1.3.1 Introduction to UMTS
1.3.1.1 Protocol layers
1.3.1.2 Access mode and frequency allocation
1.3.2 UMTS specifications for transmitters
1.3.2.1 Spectrum emission mask
1.3.2.2 Adjacent Channel Leakage Power Ratio
1.3.2.3 Spurious emissions
1.3.2.4 Error Vector Magnitude
1.4 Conclusion
Chapter 2 Digital transmitter architecture
2.1 Global transmitter architecture
2.1.1 Transmitter architecture and frequency planning
2.1.2 Digital upconversion and noise-shaping architecture
2.1.3 Power amplifier and antenna filters
2.1.3.1 Switching-mode power amplifier topology
2.1.3.2 Power DAC non-idealities
2.1.3.3 Antenna filters
2.2 UMTS implementation case of the digital transmitter
2.2.1 Proposed digital transmission chain
2.2.2 Baseband processing
2.2.3 Sample rate conversion
2.2.4 Digital Σ modulators
2.2.4.1 Lowpass Σ modulator architecture
2.2.4.2 Simulated performances
2.3 Conclusion
Chapter 3 Delta-Sigma modulator system design
3.1 Σ architecture optimization
3.2 Logic design issues
3.2.1 Critical path and digital implementation issues
3.2.2 Adder architectures analysis
3.2.3 Circuit level adders design considerations
3.3 Σ architecture with redundant arithmetic
3.3.1 Redundant number representation
3.3.2 Structures for redundant addition
3.3.3 Σ modulator architecture in BS representation
3.3.4 Simulation results
3.4 Output quantizer in Borrow-Save arithmetic
3.4.1 Non-exact quantization
3.4.2 Output signal precomputation
3.5 Conclusion
Chapter 4 Digital transmitter circuit design
4.1 Transmitter IC description
4.1.1 IC structure
4.1.2 IC configuration and layout
4.2 Sample rate conversion block design
4.2.1 Block structure
4.2.2 TSPCFF registers
4.3 Digital delta-sigma modulator circuit design
4.3.1 Global structure
4.3.2 Dynamic FA circuit description
4.3.3 Initialization circuitry
4.3.4 Σ modulator layout view
4.4 Clock generation and distribution
4.4.1 Controlled delay line description
4.4.2 Phase comparator and charge pump
4.4.3 DLL mechanism and clock signals characteristics
4.5 Digital mixer and output stages design
4.5.1 Digital mixer structure
4.5.2 Output stages
4.6 Conclusion
Chapter 5 Experimental results
5.1 First prototype IC (FULBERT I)
5.1.1 Test hardware description
5.1.1.1 Measurement tools
5.1.1.2 Test boards and assembly
5.1.2 Measurement results
5.1.2.1 Issues
5.1.2.2 Output stages measurements
5.2 Second prototype IC (FULBERT II)
5.2.1 Changes and enhancements
5.2.2 Test hardware description
5.2.3 Measurement results
5.2.3.1 Core functionality
5.2.3.2 Measurement results at a 2.6GHz main clock frequency
Frequency Spectra
ACPR vs Channel Power
SNDR vs Channel Power
EVM measurements
Output Jitter
Summary of measurements with a 2.6GHz main clock
5.2.3.3 Measurements at other frequencies
Power consumption
Evolution of ACPR
Evolution of SNDR
Evolution of EVM
Evolution of the channel power
Evolution of the jitter
Summary of measurements
5.2.4 Comparison with similar works
5.3 Conclusion
Conclusion
Parallel works
Reconfigurability
Future directions
Bibliography

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